One or more embodiments of the invention relate generally to the field of high-speed bus communications and more particularly to a method and apparatus for bus signal termination compensation via detection of a “Quiet Cycle” during normal bus operation.
Communications between devices that make up an electronic system are typically performed using one or more buses that interconnect such devices. These buses may be dedicated buses coupling only two devices, or they may be used to connect more than two devices. The buses may be formed entirely on a single integrated circuit die, thus being able to connect two or more devices on the same chip. Alternatively, a bus may be formed on a separate substrate than the devices, such as on a printed wiring board.
Modern systems such as advanced desktop and notebook computers are optimized to run at high bus speeds or bus clock frequencies, for greater performance. In such cases, proper bus signal termination, which matches the characteristic impedance of a bus line, is needed to avoid unwanted signal reflections that can interfere with bus communications.
Within advanced electronic systems, bus signal termination may be provided by on-chip termination resistors. Unfortunately, these resistors generally have an effective resistance that is not constant and instead changes as a function of several parameters, including fabrication parameters, signal voltage level, power supply voltage, and temperature. These parameters can introduce a variation in effective resistance of nearly 2:1. As a result, achieving proper termination in practice generally requires the use of on-chip, adjustable termination circuits.
Typically, the adjustable termination circuits within a manufactured device, such as a processor integrated circuit die, implement a linear compensation scheme to compensate for variations in termination resistors. In such a scheme, resistance changes are continuous (typically under the control of an analog bias voltage), rather than in discrete steps. The desired compensation may be determined, for example, by in effect measuring the resistance of the termination resistor relative to that of a reference resistor (typically an external or off-chip precision resistor), to determine the difference. This may be done during initial startup or reset of the processor, and then the on-die termination circuits are adjusted only once, prior to enabling the start of normal operation of the processor. With linear compensation schemes, it may be possible to update the termination circuit “on the fly”, that is while the bus is being used for communicating data symbols, without hampering the transmission and receipt of symbols on the bus.